Applied Materials Introduces New Technologies and Capabilities to Accelerate Heterogeneous Integration Roadmap for Semiconductor Industry
M H Santa Clara, Calif., September 8, 2021 – Applied Materials today announced new technologies and capabilities designed to help customers accelerate their technology roadmaps for heterogeneous chip design and integration.
Applied Materials combines its leadership in advanced packaging and large-area substrates with industry collaboration to accelerate solutions that deliver simultaneous improvements in power, performance, area, cost and time-to-market (PPACt).
Heterogeneous integration gives semiconductor and equipment companies a new level of flexibility in design and manufacturing by integrating chips of different technologies, functions and sizes into a single package. Applied Materials is one of the largest suppliers of advanced packaging technologies with a broad portfolio of optimized products covering etch, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, surface treatment and annealing technologies. Applied’s Advanced Packaging Development Center in Singapore has the industry’s broadest product portfolio, including advanced bumping, microbumping, precision wire redistribution layers (RDL), through-silicon vias (TSV), and hybrid bonding. The integration has laid a solid foundation.
Heterogeneous integration gives semiconductor and equipment companies a new level of flexibility in design and manufacturing by integrating chips of different technologies, functions and sizes into a single package. Applied Materials combines process and large-area substrate leadership with an ecosystem to accelerate the industry’s heterogeneous design and integration roadmaps.
“Applied’s industry-leading portfolio of advanced packaging solutions provides customers with a broad choice of enabling technologies for heterogeneous integration,” said Nirmalya Maity, group vice president, Advanced Packaging, Applied Materials. Working together, we have built an ecosystem that accelerates our customers’ PPACt roadmaps and creates exciting new growth opportunities for our company.”
Today, Applied Materials unveiled a number of innovations in three key areas of advanced packaging for heterogeneous integration: chip-to-wafer hybrid bonding, wafer-to-wafer bonding, and advanced substrates.
Accelerates die-to-wafer hybrid bonding
Hybrid chip-to-wafer bonding uses copper-to-copper direct interconnects to increase I/O density and reduce wire lengths between chiplets, thereby improving overall performance, power, and cost. To accelerate the development of this technology, Applied Materials is enhancing advanced software modeling and simulation capabilities for its Advanced Packaging Development Center. These capabilities enable various parameters such as material selection and package architecture to be evaluated and optimized prior to hardware development, significantly reducing learning cycles and accelerating time-to-market for customers. This is all thanks to the joint development agreement between Applied Materials and BE Semiconductor Industries NV (Besi) announced in October 2020 to develop the industry’s first proven complete Device Solutions.
Ruurd Boomsma, CTO of Besi, said: “Our joint development program with Applied Materials has deepened our understanding of co-optimized equipment solutions, helping us meet customer needs and enabling customers to use complex Hybrid bonding process. Besi and Applied Materials’ Hybrid Bonding Center of Excellence team in Singapore have worked together, and the technology has advanced by leaps and bounds in a short period of time, not only optimizing the processing of customer materials, but also accelerating the development of advanced heterogeneous integration technology. “
Develop a co-optimized solution for hybrid wafer-to-wafer bonding
Wafer-to-wafer bonding enables chipmakers to build certain chip structures on one wafer and other different chip structures on the other, and then bond the two wafers to create a complete device. In order to achieve high performance and high yield, it is critical to ensure the quality of the front-end process steps, and ensure the uniformity and wafer alignment accuracy during wafer bonding. Applied Materials today announced a joint development agreement with EV Group (EVG) to develop co-optimized solutions for wafer-to-wafer bonding. Applied Materials has extensive expertise in deposition, planarization, ion implantation, measurement, and inspection processes in semiconductor processing, while EVG has extensive experience in wafer bonding, wafer preconditioning and activation, and measurement of bond stacks. The industry’s leading position, this collaboration can organically combine the advantages of the two.
Dr. Thomas Uhrmann, Director of Business Development at EVG, said: “3D integration and materials engineering are helping the semiconductor industry continue to innovate, driving the increasing demand for wafer hybrid bonding. Optimizing this critical process for new application areas requires in-depth Understand various integration issues in the upstream and downstream of the process chain. Through industry collaboration, different process equipment companies can not only share data, but also learn from each other’s respective areas of advantage, learn from others’ strengths, and synergistically optimize solutions to better serve Customers solve a variety of new critical manufacturing challenges.”
Vincent DiCaprio, general manager of advanced packaging business development at Applied Materials, said: “Our collaboration with industry partners, including Besi and EVG, provides customers with the capabilities and expertise they need to accelerate development and deployment, including chip-to-wafer. Hybrid bonding technologies including wafer-to-wafer. The number of chipmakers using heterogeneous design technologies to drive the PPACt roadmap continues to increase, and Applied Materials is looking forward to building deeper within the ecosystem with customers and partners interaction and collaboration.”
Larger, more advanced substrates help optimize PPACs
As chipmakers continue to try to fit more and more chips into complex 2.5D and 3D package designs, the need for more advanced substrates is increasing. To expand package size and increase interconnect density, Applied Materials uses cutting-edge panel-level process technology from its recently acquired Tango Systems. Panel-sized substrates measure no smaller than 500mm x 500mm and can accommodate more packages than wafer-size specifications, optimizing power, performance and area while saving costs.
For customers using larger panel size substrates, Applied Materials provides large-area materials engineering technologies from the Display business unit, including deposition, electron beam testing, scanning electron microscope (SEM) inspection and measurement, and for defect analysis focused ion beam technology.
Applied Materials explored the company’s packaging technologies in further detail at the 2021 ICAPS and Packaging Masterclass on September 8.
The Links: PG640400RA4-3 BCM62B215 6MBI25J-120
